ECP5 plans for the near future

2020-2-20

I got the ECP5 EVN development board for the ECP5 LFE5UM5G-85F-8BG381 FPGA now and I found out that it can be clocked a bit faster than the specs, a 30 bit counter works on like 800+ MHz, at 900 MHz the last two bits glitch.
Now I want to see whether I can get a gigabit over a differential pair, since that would allow an ADC like the HMCAD1511 to be used.
The differential pairs will use double data rate, so that only 500 MHz will be needed which leaves enough room. The internal PLL of the FPGA can generate to nearly 1 GHz, which is enough for the DDR input but not for the ADC.
Further using the SERDES for PCIe 2.0 would be nice, there's already a project working on that in nmigen but it didn't have a commit in nearly a year, though it could provide a good point to start off of.
I got the ECP5 EVN development board for the ECP5 LFE5UM5G-85F-8BG381 FPGA now and I found out that it can be clocked a bit faster than the specs, a 30 bit counter works on like 800+ MHz, at 900 MHz the last two bits glitch.
Now I want to see whether I can get a gigabit over a differential pair, since that would allow an ADC like the HMCAD1511 to be used.
The differential pairs will use double data rate, so that only 500 MHz will be needed which leaves enough room. The internal PLL of the FPGA can generate to nearly 1 GHz, which is enough for the DDR input but not for the ADC.
Further using the SERDES for PCIe 2.0 would be nice, there's already a project working on that in nmigen but it didn't have a commit in nearly a year, though it could provide a good point to start off of.




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